1. Field of the Invention
The present invention relates to an instruction cache system, an instruction-cache-system control method, and an information processing apparatus that adopt a set associative system.
2. Description of the Related Art
Conventionally, to improve a hit ratio of an instruction cache, a set associative system using a plurality of ways has been mainly adopted in instruction cache systems in which the instruction cache is placed in a processor. In the instruction cache system adopting the conventional set associative system, there is a problem in that it is difficult to expand the ways after the instruction cache is once installed in the processor. For example, a technique enabling to increase the number of ways temporarily at the time of operation is disclosed in Japanese Patent Application Laid-Open No. H6-231044. However, with this technique, auxiliary caches need to be arranged beforehand, which is considerably disadvantageous in view of the installing area and cost.
Further, when an instruction code is prefetched in the conventional instruction cache system, there is a problem in that any of cache lines needs to be removed from the instruction cache or a separate buffer memory for prefetch needs to be arranged near the instruction cache.